1. Field of the Invention
The invention relates generally to the field of electronic circuits and more particularly to systems and methods for improving the structure and operation of variable timing circuits that are constructed using silicon-on-insulator (SOI) technology.
2. Related Art
There are times when it is useful in an electrical circuit to be able to delay a signal by a variable amount of time. For example, if a particular circuit is activated by the overlap of pulses in two different received signals, it may be desirable to control the timing of at least one of the signals in order to control the overlap of the pulses and thereby control the activation of the circuit. The variable delay can be implemented, for instance, in a logic circuit such as that one depicted in FIG. 1.
Referring to FIG. 1, a diagram illustrating the design of an exemplary variable-delay circuit in accordance with the prior art is shown. Variable delay circuit 100 consists of Variable delay circuit 100 consists of a set of inverters and NAND gates that are configured to delay a signal received on input line 161 by a variable amount of time and to provide the delay output signal on output line 162. The amount of time by which the received signal is delayed is dependent upon a set of select signals that are also input to circuit 100.
Depending upon which of the select signals is asserted, the signal input on line 161 is passed through a fixed set of logic components, and potentially through one or more additional sets of logic components. These components correspond to a “fixed” portion and a variable portion of the total delay through circuit 100. Thus, if signal select2 is asserted (and signals select1 and select0 are de-asserted,) the signal input on line 161 passes through inverters 111 and 112, NAND gates 123 and 151, and inverters 152 and 153 before being output on line 162 with the minimum, “fixed” delay. If signal select1 is asserted (and signals select2 and select0 are de-asserted,) the signal input on line 161 passes through inverters 111 and 112, NAND gates 122 and 141, inverter 142, NAND gate 151 and inverters 152 and 153 before being output on line 162. In this instance, the total delay consists of the “fixed” delay, plus the delay through the two additional logic gates, 141 and 142. If signal select0 is asserted (and signals select1 and select2 are de-asserted,) the signal input on line 161 passes through inverters 111 and 112, NAND gates 121 and 131, inverter 132, NAND gate 141, inverter 142, NAND gate 151 and inverters 152 and 153 before being output on line 162. In this case, the total delay consists of the “fixed” delay, the additional delay incurred with the assertion of select1, and the delay corresponding to two additional logic gates, 131 and 132.
Typically, it is desirable to increase the speed, including circuits that include variable-delay circuits such as the one described above. One way to achieve this goal is to use silicon-on-insulator (SOI) technology to manufacture the circuits. Transistors that are manufactured using SOI technology can be faster than transistors that are constructed directly on a silicon substrate. Logic gates that are built with these transistors, hence the circuits that use these logic gates, can therefore also be smaller and faster than their non-SOI counterparts.
The use of SOI technology can have drawbacks, however. For example, because the transistors are built on an insulating substrate, the bodies of the transistors typically “float.” The body voltages of the transistors may therefore be different at different times. For example, if a transistor is coupled to a node that may alternately be at Vdd or at ground, the body voltage of the transistor may be pulled toward the node voltage. The body voltage will therefore typically be somewhere between the high and low voltages that can be present at the node to which the transistor is coupled. Because, in a logic circuit, the voltage at the node may vary irregularly between high and low values corresponding to binary data values that are represented by the node over time, the body voltage of the transistor is dependent on the history of the voltages at the node. In other words, the body voltage of the transistor is dependent upon the history of the node. This is referred to as the history effect.
The fact that SOI-based transistors may be subject to the history effect is important because the threshold voltage of each transistor varies with the body voltage of the transistor. This, in turn, is important because the response of the transistor (e.g., the delay with which the transistor switches) varies with the threshold voltage of the transistor. The transistor response is therefore dependent, to some extent, upon the previous state (the history) of the circuit in which it is used. Thus, the response of SOI components of a variable-delay circuit such as the one described above may have varying responses that result in variations in the delays that can be selected for the circuit.